Dynamic Staff Design Verification Engineer with nearly 10 years experience at Qualcomm, specializing in UVM and System Verilog for WiFi IPs. Have experience of end to end IP verification for at least 6 complicated IPs.
Proven leader of a 10-engineer team, successfully delivering 4 projects while excelling in formal verification and project leadership.
Have an overall industry experience of 12 years
ASIC IP level Verification Manager from Qualcomm with 9+ years of experience in UVM and System Verilog based functional Verification of WiFI based IPs that work on MAC level.
Leading a team of 10 engineers , have successfully delivered 4 projects over the last 3 years owning and managing important IP tiles in Wifi.
As a Senior IP DV Engineer , took up ownership of 3 important IPs at WifI MAC and successfully delivered Verified RTL over multiple important WiFi projects at MAC level.
Got timely promotions over the 6 year tenure from Junior to senior to lead.
Joined as Fresh college Grad through campus placements. Gained 1 year experience in scripting and 1 year with RTL design and linting. Got rolled over as Full time employee in 2015
UVM
System Verilog
Testplanning
End to end design verification
Formal property DV
Project leadership
People management
System C Modelling
Performance DV