Summary
Overview
Work History
Education
Skills
Milestones
Languages
Timeline
Generic
Balaji Vishwanath

Balaji Vishwanath

Chennai

Summary

Dynamic Staff Design Verification Engineer with nearly 10 years experience at Qualcomm, specializing in UVM and System Verilog for WiFi IPs. Have experience of end to end IP verification for at least 6 complicated IPs.

Proven leader of a 10-engineer team, successfully delivering 4 projects while excelling in formal verification and project leadership.


Have an overall industry experience of 12 years

Overview

12
12
years of professional experience

Work History

Staff Design Verification Engineer/ Manager

Qualcomm
06.2021 - Current

ASIC IP level Verification Manager from Qualcomm with 9+ years of experience in UVM and System Verilog based functional Verification of WiFI based IPs that work on MAC level.

Leading a team of 10 engineers , have successfully delivered 4 projects over the last 3 years owning and managing important IP tiles in Wifi.


Senior Asic Verification Engineer

Qualcomm
05.2015 - 04.2021

As a Senior IP DV Engineer , took up ownership of 3 important IPs at WifI MAC and successfully delivered Verified RTL over multiple important WiFi projects at MAC level.

Got timely promotions over the 6 year tenure from Junior to senior to lead.

Associate Engineer

Zilogic Systems Pvt Ltd Contracted to Qualcomm Inc
04.2013 - 04.2015

Joined as Fresh college Grad through campus placements. Gained 1 year experience in scripting and 1 year with RTL design and linting. Got rolled over as Full time employee in 2015

Education

Bachelor of Engineering - Electrical, Electronics And Communications Engineering

PSG College of Technology
04-2013

High School Diploma -

Venkatalakshmi Matriculation School
04-2009

Skills

UVM

System Verilog

Testplanning

End to end design verification

Formal property DV

Project leadership

People management

System C Modelling

Performance DV

Milestones

Languages

english
Bilingual or Proficient (C2)
Tamil
Bilingual or Proficient (C2)

Timeline

Staff Design Verification Engineer/ Manager

Qualcomm
06.2021 - Current

Senior Asic Verification Engineer

Qualcomm
05.2015 - 04.2021

Associate Engineer

Zilogic Systems Pvt Ltd Contracted to Qualcomm Inc
04.2013 - 04.2015

Bachelor of Engineering - Electrical, Electronics And Communications Engineering

PSG College of Technology

High School Diploma -

Venkatalakshmi Matriculation School
Balaji Vishwanath